In conventional TTL logic device, there is a propagation delay between the application of a binary signal to an input terminal and the result produced at an output terminal. The propagation delay is a result of the time required to change the direction or phase of current in the presence of stray capacitance in circuit elements and related components capable of storing charge. In high speed integrated circuits, such concerns are significant.
In the past, there have been a number of techniques for reducing propagation delays. One technique has been the amount of current used to steer the switching elements. Another technique has been to provide speed up diodes for discharging capacitance internal to the circuit device. Still another way has been to employ circuit elements which are inherently faster such as Schottky-type diodes and transistors which are inherently faster than conventional transistors.
Referring to FIG. 1, there is shown a prior art embodiment of a conventional high speed TTL logic gate 10. The gate 10 employs Schottky circuit elements for speed. All nodes and elements have been numbered for convenience of reference. Conventional circuit designations are employed to designate the elements.
A "pullup" subcircuit for providing current from a higher level voltage V.sub.CC, which corresponds to a binary ONE (positive logic), comprises transistors Q3 and Q4 forming a Darlington coupled between node 7 and node 9, node 9 being the output terminal of the gate and node 7 being either an optional current limiting resistor R4 or a short circuit to node 6 coupled at the voltage source V.sub.CC.
A subcircuit for "pull" of the output terminal node 9 to the ground node 11 comprises a transistor Q5 and resistor R3. A conventional squaring network (not shown) may optionally be substituted for the resistor R3.
A phase splitter subcircuit comprises a transistor Q2 which receives at its base a data signal input from a single or multiple emitter transistor Q1 through node 3 and which is operative to control the pullup and pulldown node 9.
In operation, when a binary ZERO or low level voltage appears at either input 1A or 1B, a low voltage appears at the base of Q2, namely at node 3, preventing transistor Q2 from conducting between its collector and emitter. The voltage at node 5 at the emitter therefore drops toward the ground level and the voltage at node 4 at the collector rises toward the V.sub.CC level. The high level appearing at the base of transistor Q3 permits transistor Q3 to begin to conduct to the base of transistor Q4, which in turn conducts current from V.sub.CC to the output at node 9. The voltage level at node 9 therefore moves toward the V.sub.CC level, generating a binary ONE.
When a binary ONE appears at both of the input terminals 1A and 1B, the output voltage goes to a binary ZERO according to the following mechanism. With a binary ONE appearing at the input, transistor Q1 becomes non-conducting, and the voltage at the base of Q2 goes toward V.sub.CC. The rise in the base-to-emitter voltage between node 3 and node 5 causes transistor Q2 to begin to conduct, sinking current from the base of transistor Q3 to turn off transistor Q3 and transistor Q4. Current from the high level voltage V.sub.CC is cut off from node 9, and transistor Q5 becomes conductive of current from node 9 to the ground 11 in order to dissipate whatever current load may be coupled to the output terminal at node 9.
The speed with which the transistor Q5 discharges the load drawing the output level at node 9 to the low level voltage toward ground depends on the base current delivered from node 5 to transistor Q5, which is dependent on the current characteristic of transistor Q5. Transistor Q5 and related resistor R3 must sink current not only from the load capacitance between the output node 9 and ground 11 but also any internal parasitic capacitances associated with the components in the structure of the device, represented here by capacitance element 12.
To speed up the discharge of the internal capacitances, speedup diodes D1 and D2 are provided, speedup diode D1 being coupled between node 8 and node 4 and speedup diode D2 being connected between node 9 and node 4 to be forward biased when nodes are at a voltage level higher than the voltage at node 4.
Speedup diode D1 is operative to discharge the base of transistor Q4 while speedup diode D2 is operative to divert some of the discharging load current at node 9 to the collector of transistor Q2. The resultant increased emitter current of transistor Q2 becomes the base drive current to pulldown transistor Q5. It is the purpose of this additional drive current routed through speedup diode D2 to sink current from the output node 9 even faster than would be normal in the absence of such speedup diodes as D1 and D2.
While speedup diodes enhance the switching speed of such high speed gates, the speedup diodes D1 and D2 increase the stray capacitance (capacitance element C1) of node 4 at least partly contributing to the proolem of undesired or stray capacitance which slows switching. Furthermore, by the inherent nature of silicon diodes, the speedup diodes D1 and D2 do not turn on until a forward bias of at least 0.7 volts has developed between node 8 or node 9 and node 4. Thus, until the voltage at node 4 has dropped considerably, the speedup diodes present a hindrance rather than a help to circuit operation speed. What is therefore needed is a mechanism for enhancing the switching speed of a high speed gate without the disadvantages of increased stray capacitance and a relatively high internal bias required of speedup circuitry.